The disclosures herein relate generally to information handling systems and more particularly to processor interrupt techniques associated with such systems.
Devices in an information handling system typically employ interrupts to notify one or more processors that a particular device in the system requires attention. Early personal computer systems employed the so-called Industry Standard Architecture (ISA) bus in which devices could not share interrupts. In contrast, the more recent Peripheral Component Interconnect (PCI) bus employs sharable interrupts. In the PCI bus architecture, two or more devices fixed to the motherboard or devices plugged into expansion slots on the motherboard may share the same interrupt.
System designers can distribute PCI interrupts based on the topology of the fixed devices soldered down on the motherboard, such as integrated video and an integrated network interface, to assure that interrupts (IRQ's) are distributed evenly across such devices. However, designers can neither control nor predict which PCI expansion slots will be populated with devices by the user or others This often results in an inefficient interrupt (IRQ) distribution among the devices plugged into expansion slots whereby some interrupts carry a larger burden than other interrupts. While in such a system, if many devices are assigned to a particular sharable interrupt, the system will still function, although significant delays will be experienced while the system polls to see from which particular device the shared interrupt originated.
What is needed is a mechanism to balance IRQ's among fixed devices on the motherboard and which accounts for the scenario where a subset of expansion slots are populated with devices installed by the user or others. Balancing of IRQ's across all of these fixed devices and later installed expansion devices is desirable to decrease device latency or response times. It is known to employ PIIX (PCI ISA IDE Accelerator) and ICH (I/O Controller Hub) routing logic to map PCI interrupts to ISA interrupts; however, unfortunately this does not address the IRQ balancing problem at hand.